Performance Investigation of Bottom Gate ZnO Based TFT for High-Speed Digital Display Circuit Applications

This paper explores possibility of device as well as circuit performance enhancement in the bottom gate ZnO based TFT via Mg and Cd material doping. DC, Analog & RF performance, Energy efficiency and Noise analysis were performed for both doped (i.e., MgyZn1-yO and CdxZn1-xO) and undoped ZnO channel TFT structures. Further, successful circuit implementation of these devices was done in resistive inverter and AMLCD pixel display circuits. Performance wise both MgyZn1-yO and CdxZn1-xO channel TFTs were found to be superior against its undoped variant. 376%, 105% and 162% are the percentage improvement in (I-ON/I-OFF) ratio, field effect mobility mu(mu FE) and effective mobility mu(mu eff) for CdxZn1-xO based TFT with respect to ZnO based TFT, same parameters show 194%, 103% and 133% percentage improvement for the case of MgyZn1-yO TFT. Also, 23% is percentage decrease in subthreshold swing (SS) for CdxZn1-xO based TFT with respect to ZnO based, whereas 11% is percentage decrement for MgyZn1-yO. Intrinsic gate delay, the percentage decrement is 54.15 and 59.95% for MgyZn1-yO and CdxZn1-xO respectively w.r.t ZnO. Both the CdxZn1-xO and MgyZn1-yO TFT shows unanimous decrease in delay for the resistive inverter as well as AMLCD pixel display circuits. The reported results shows that bottom gate CdxZn1-xO TFT has better performance for above-mentioned performance parameters. The numerical simulations are performed on Silvaco ATLAS TCAD simulator.