Stimuli Generation for IC Design Verification using Reinforcement Learning with an Actor-Critic Model

With Integrated Circuit (IC) designs becoming larger and more complex, there is a growing risk of errors in the Register-Transfer Layer (RTL) implementation. Stimuli generation to achieve high coverage in functional verification is paramount for finding these errors and preventing them from ending up in the final design. Several custom methods have been proposed for stimuli generation to reduce functional testing duration of RTL designs, while more flexible or generic methods could reduce verification time significantly by supporting larger range of RTL designs. This paper proposes a novel flexible stimuli generation technique by using reinforcement learning with an Actor-Critic model. Our benchmarking results showed that the proposed method achieves a higher coverage than baseline solution for a diverse range of RTL designs, making it a valuable addition to test automation tool-flow.