Design of a Low-Power and Area-Efficient LDO Regulator Using a Negative-R-Assisted Technique

To mitigate the non-ideal virtual ground at the feed-back node of a low dropout (LDO) regulator, this brief presents an LDO with an off-chip capacitor that uses a negative-R assisted technique, which enhances its performance, including load/line regulation and power supply rejection (PSR). This technique enables the LDO to achieve improved performance despite the small size of the pass transistor, resulting in low-power and area-efficient LDO regulators. The proposed negative-R-assisted LDO provides 100 mA, with load regulation of 0.09 mV/mA, line regulation of 6 mV/V, and PSR of -31 dB. The proposed negative-R-assisted LDO was implemented with 150 nm transistors in a28 nm standard CMOS process with an active area of 4,200 mu m(2).The proposed LDO achieves a superior figure-of-merit (FoM) of 13.5 ps (FoM1) and 0.057 ps<middle dot>mm(2)(FoM2).