A Lightweight Scan Architecture against the Scan-based Side-channel Attack

The demand for cryptographic chips is growing rapidly in the market nowadays. Chips must undergo rigorous testing in order to promote quality. Scan-based design for testability (DFT) is widely used to improve the quality of testing. However, scan chain technology also provides illegal users with convenience. They can steal sensitive information of circuit under test (CUT) during testing, which seriously threatens the security of IP cores. Currently, researchers have proposed many secure strategies, but most of them affect the test quality or cause larger hardware overhead. In this paper, we propose a lightweight scan architecture against the scan-based side-channel attack. In this method, a number of logic gates, a linear feedback shift register (LFSR) and two corresponding counters are integrated into the design in order to ensure the security of the design. The normal scan operation can be performed only if users enter the correct scan input key at the K clock cycles. Otherwise, the scheme will incur scan obfuscation. Therefore, illegal users can only observe some incorrect responses from the scan output port. It is known from simulation results and theoretical analysis that the scheme is able to successfully defend against the scan-based side-channel attack while having extremely low overhead and high testability.