High Performance and Hardware-Efficient Approximate BPF Decoder for Polar codes

Belief propagation flip (BPF) decoding is a modified algorithm of BP decoding for polar codes, which has the error correction capability comparable to successive cancellation list (SCL) decoding while retaining the high throughput performance of BP decoding. However, the high complexity of BPF decoding algorithm limits its efficiency and maximum working frequency in hardware implementation. In this paper, a comprehensive BPF (CBPF) scheme is proposed by considering multi-factors affecting the selection of bits to be flipped. Additionally, two type processing elements (PEs) units in the decoders are proposed to reduce the latency. To further enhance the maximum working frequency and reduce the hardware efficiency, a parallel log-likelihood ratio (LLR) sorter using approximate computation is proposed. The proposed CBPF decoder with 1024 code length and 1/2 code rate is implemented on a 28nm CMOS technology, which achieves throughput of 20.48Gb/s at Eb/N0 = 4.0 dB with area occupied only 0.537mm(2). Simulation results show that the proposed decoder has higher hardware efficiency and fairly good error correction performance compared to the state-of-the-art works.