An Aging Small-Signal Equivalent Circuit Modeling Method for InP HBT

被引：0
|
作者：
Cheng, Lin [1 ,2 ]
Lu, Hongliang [1 ,2 ]
Yan, Silu [1 ,2 ]
Qi, Junjun [1 ,2 ]
Cheng, Wei [3 ]
Zhang, Yuming [1 ,2 ]
Zhang, Yimen [1 ,2 ]
机构：
[1] Xidian Univ, Sch Microelect, Xian 710071, Peoples R China
[2] Xidian Univ, Key Lab Wide Band Gap Semicond Technol, Xian 710071, Peoples R China
[3] Nanjing Elect Devices Inst, Sci & Technol Monolith Integrated Circuits & Modul, Nanjing 210016, Peoples R China
来源：
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2023年 / 23卷 / 04期
关键词：
Heterojunction bipolar transistor; aging small-signal equivalent circuit model; key model parameters; aging sensitivity; RELIABILITY;
D O I：
10.1109/TDMR.2023.3323899
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
To predict the aging effect on indium phosphide (InP) heterojunction bipolar transistors (HBTs), an aging small-signal equivalent circuit modeling method is proposed in this paper, with special attention to the degradation of the key small-signal model parameters of the InP HBTs in aging experiments. Based on the analysis of the aging sensitivity of the complete small-signal equivalent circuit parameters, semi-empirical approach is used to model the degradation of the key parameters in bipolar transistors as a function of stress magnitude and stress time. Its validity and accuracy are demonstrated by comparison of the modeled and measured results for InP HBTs before and after degradation.
引用
收藏
页码：530 / 536
页数：7
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