Generalized Modulation of Common Mode Voltage Reduction for Current Source Inverter in Balanced and Unbalanced Load Cases

The common mode voltage (CMV) has been extensively investigated as a significant issue under balanced voltage conditions. However, in practical applications, voltage asymmetry caused by load imbalance can lead to an increase in the magnitude of CMV. Therefore, in the presence of load imbalance, it is necessary to adjust the arrangement of switch state to control the output voltage, and redesign the CMV suppression strategy. To overcome these issues, this article proposes a general modulation aimed at suppressing CMV in two cases: balance and unbalanced load. Compared with traditional space vector modulation (SVM), the proposed modulation can reduce the peak of CMV to approximately 43.3%-50% under the balanced load and 50% under the unbalanced load. In addition, although three-dimensional SVM (3-D SVM) is a common modulation strategy for four-leg inverters, it suffers from computationally complex problems in its implementation. Therefore, a simplified method is proposed based on 3-D SVM. After being simplified, the calculation time of the modulation can be reduced. Then, a comprehensive comparison is conducted between the proposed and other modulation strategies. Finally, a four-leg CSI is built in the laboratory. Experimental and simulation results verify the effectiveness of the proposed method under balanced and unbalanced load conditions.