Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications

被引:0
|
作者
Yan, Aibin [1 ]
Chang, Yang [1 ]
Xiang, Jing [1 ]
Luo, Hao [1 ]
Cui, Jie [1 ]
Huang, Zhengfeng [2 ]
Ni, Tianming [3 ]
Wen, Xiaoqing [4 ]
机构
[1] Anhui Univ, Hefei, Peoples R China
[2] Hefei Univ Technol, Hefei, Peoples R China
[3] Anhui Polytech Univ, Wuhu, Peoples R China
[4] Kyushu Inst Technol, Fukuoka, Japan
关键词
SRAM; soft error; double-node-upset; self-recoverability; SINGLE;
D O I
10.1145/3583781.3590261
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this paper, we propose two Highly Reliable and High-Speed SRAM cells, namely HRHS18T and HRHS18T_EV. The proposed cells can be applied to safety-critical applications due to their excellent self-recoverability from node-upsets. Meanwhile, the proposed cells have smaller read/write delay than other state-of-the-art hardened SRAMs. Simulation and quantitative calculation results show that, the proposed HRHS18T cell can save 65.05% read time and 38.12% write time at the cost of 51.89% power consumption and 32.69% area on average compared with alternative SRAMs. The results also show that the HRHS18T_EV cell can save 65.05% read time and 73.28% write time at the cost of 51.89% power consumption and 32.69% area on average compared with alternative SRAMs.
引用
收藏
页码:293 / 298
页数:6
相关论文
共 50 条
  • [31] Evaluating the contribution of desktopVR for safety-critical applications
    Johnson, C
    COMPUTER SAFETY, RELIABILITY AND SECURITY, 1999, 1698 : 67 - 78
  • [32] A practical implementation of BICS for safety-critical applications
    Smith, PA
    Campbell, DV
    2000 IEEE INTERNATIONAL WORKSHOP ON DEFECT BASED TESTING, PROCEEDINGS, 2000, : 51 - 56
  • [33] Use of modern processors in safety-critical applications
    Bate, I
    Conmy, P
    Kelly, T
    McDermid, J
    COMPUTER JOURNAL, 2001, 44 (06): : 531 - 543
  • [34] BICMOS CIRCUIT TECHNOLOGY FOR A HIGH-SPEED SRAM
    DOUSEKI, T
    OHMORI, Y
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (01) : 68 - 73
  • [35] A safety analysis framework for COTS microprocessors in safety-critical applications
    Lee, Jason D.
    Bliojwani, Praveen S.
    Mahapatra, Rabi N.
    HASE 2007: 10TH IEEE HIGH ASSURANCE SYSTEMS ENGINEERING SYMPOSIUM, PROCEEDINGS, 2007, : 407 - 408
  • [36] HIGH-SPEED SAFETY
    KRECHMER, K
    BYTE, 1991, 16 (04): : 143 - &
  • [37] High-Speed Reliable Data Transfer for Distribution Smart Grid Applications
    Hrnjic, Tarik
    Donlagic, Tarik
    2016 XI INTERNATIONAL SYMPOSIUM ON TELECOMMUNICATIONS (BIHTEL), 2016,
  • [38] Nanoprober pulse testing: Nanoprobing SRAM bit cells with high-speed pulses
    Zyvex Instruments LLC, United States
    Electron. Device Fail. Anal., 2009, 4 (22-27):
  • [39] Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications?
    Sabena, D.
    Sterpone, L.
    Schoerlzel, Mario
    Koal, Tobias
    Vierhaus, H. T.
    Wong, S.
    Glein, R.
    Rittner, F.
    Stender, C.
    Porrmann, M.
    Hagemeyer, J.
    2014 19TH IEEE EUROPEAN TEST SYMPOSIUM (ETS 2014), 2014,
  • [40] Part marking and material applications on safety-critical and high-cost parts
    Jemison, Patrick W.
    Goes, Christopher M.
    Yates, Jeffery A.
    ANNUAL RELIABILITY AND MAINTAINABILITY SYMPOSIUM, 2007 PROCEEDINGS, 2006, : 473 - +