An Optimized Device Structure with Improved Erase Operation within the Indium Gallium Zinc Oxide Channel in Three-Dimensional NAND Flash Applications

In this paper, we propose an optimized device structure to address issues in 3D NAND flash memory devices, which encounter difficulties when using the hole erase method due to the unfavorable hole characteristics of indium gallium zinc oxide (IGZO). The proposed structure mitigated the erase operation problem caused by the low hole mobility of IGZO by introducing a filler inside the IGZO channel. It facilitated the injection of holes into the IGZO channel through the filler, while the existing P-type doped polysilicon filler material was replaced by a P-type oxide semiconductor. In contrast to polysilicon (band gap: 1.1 eV), this P-type oxide semiconductor has a band gap similar to that of the IGZO channel (2.5 to 3.0 eV). Consequently, it was confirmed through device simulation that there was no barrier due to the difference in band gaps, enabling the seamless supply of holes to the IGZO channel. Based on these results, we conducted a simulation to determine the optimal parameters for the P-type oxide semiconductor to be used as a filler, demonstrating improved erase operation when the P-type carrier density was 1019 cm-3 or higher and the band gap was 3.0 eV or higher.