Resource-efficient RISC-V Vector Extension Architecture for FPGA-based Accelerators

For the increasing demands of embedded computation, hardware accelerators are widely used with processors. FPGA provides flexibility to design such accelerators because it is a programmable device. But developing a custom accelerator for each application is time-consuming and not reusable. On the other hand, vector processing brings the opportunity to accelerate computation by taking advantage of data-level parallelism. This paper presents the architecture of a scalable soft Vector Processing Unit for FPGA based on a subset of the RISC-V vector extension instruction set. Maximum vector length and the number of lanes are configurable in the proposed architecture. We have integrated our proposed vector processing unit into a 32-bit scalar RISC-V core and implemented it in FPGA. The implementation result shows that our proposed architecture consumes significantly less FPGA resources and has more than four times frequency improvement than other vector processing units. It achieves 11.9 giga operation per second for 8-bit integer convolution operation. We demonstrate that the performance of the proposed vector processing unit is scalable with maximum vector length and the number of lanes.