Machine Learning Driven Synthesis of Clock Gating

One of the key issues in the synthesis of clock gating is how the flip-flops with similar activity patterns in the target design are identified and grouped, so that all flip-flops in each group should be clock-gated in a way to make a full effectiveness in power saving. As yet, due to the excessive runtime and explosive memory usage demand, the conventional grouping methods have relied on flip-flops' toggling probability or toggling pattern of 'short' length, which clearly results in the power saving far off that of the optimal grouping. In this work, we overcome this limitation by proposing a machine learning (ML) based flip-flop grouping for clock gating. Precisely, we devise (1) a convolutional autoencoder (CAE) model to produce a 'short' embedding vector corresponding to the 'very long' input activity pattern of every flip-flop, (2) a convolutional neural network (CNN) based ranker model to predict the degree of flip-flop activity similarity between two input embedding vectors, and (3) a CNN-based model to produce an embedding vector that combines two input embedding vectors. Then, we propose an ML based clock gating synthesis algorithm, which is able to reduce the total dynamic power on circuits by 6.3% further on average over that by the conventional state-of-the-art clock gating with no timing violation by the gated logic delay as well as the satisfaction of physical proximity constraint on flip-flops for clock gating.