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- [2] Enhanced Barrier Seed Metallization for Integration of High-Density High Aspect-Ratio Copper-Filled 3D Through-Silicon Via Interconnects 2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 822 - 826
- [6] Analysis of high aspect ratio Through Silicon Via (TSV) diffusion and stress impact profile during 3D advanced integration SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 4, 2014, 61 (03): : 219 - 226
- [7] Optimization of Chemistry and Process Parameters for Void-Free Copper Electroplating of High Aspect Ratio Through-Silicon Vias for 3D Integration 2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, : 1301 - +
- [8] Highly-Conformal Plasma-Enhanced Atomic-Layer Deposition Silicon Dioxide Liner for High Aspect-Ratio Through-Silicon Via 3D Interconnections 2012 4TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), 2012,
- [9] Replacing the PECVD-SiO2 in the Through-Silicon Via of High-Density 3D LSIs with Highly Scalable Low Cost Organic Liner: Merits and Demerits 2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2014, : 636 - 640