Optimization of Chemistry and Process Parameters for Void-Free Copper Electroplating of High Aspect Ratio Through-Silicon Vias for 3D Integration

The through-silicon via is a key element in the development of 3D integration technology for new generations of advanced electronic systems. There are several challenges associated with filling these deep, relatively large diameter vias using standard copper electroplating processes, like those common in damascene technology. This paper will summarize a process development for copper electroplating of deep silicon vias in the range of 20-200 mu m in diameter and 150-375 mu m in depth. The test vias had aspect ratios ranging from 1.3:1 to 8:1, with sidewalls which were approximately vertical. The paper will discuss copper via plating results with respect to additive component levels, current density, seed layer quality, and sample pretreatments pertaining to wetting of the vias in the plating solution.