1T DRAM with Raised SiGe Quantum Well for Sensing Margin Improvement

被引：2
|
作者：
Lee, Si-Won [1 ]
Cho, Seongjae [2 ]
Cho, Il Hwan [1 ]
Kim, Garam [1 ]
机构：
[1] Myongji Univ, Dept Elect Engn, Yongin 17058, South Korea
[2] Gachon Univ, Dept Elect Engn, Seongnam 13120, South Korea
来源：
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | 2023年 / 23卷 / 01期
基金：
新加坡国家研究基金会;
关键词：
Index Terms-One-transistor (1T) dynamic random-access memory (DRAM); sensing margin; technology computer-aided design (TCAD); LOW-POWER; GATE; TRANSISTOR; TECHNOLOGY;
D O I：
10.5573/JSTS.2023.23.1.64
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a novel one-transistor dynamic random-access memory (1T DRAM) with a raised SiGe quantum well (QW) under one gate in the double-gate (DG) structure is proposed. The proposed structure can improve the poor performance of the retention time and sensing margin which is the problem of the conventional 1T DRAM. In write operation, the performance is improved through the band to band tunneling (BTBT) between body and drain and through valence band offset between SiGe and Si. Also by utilizing the physical barrier of oxide, read "1" retention time can be increased. The fabrication process is also proposed.
引用
收藏
页码：64 / 70
页数：7
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