Hardware-Efficient Design and Implementation of a Spiking Neural Model With Noisy Astrocyte

Neuromorphic architectures are systems that aim at using the principles of biological neural functions as their basis of operation. One of the most significant challenges in neuromorphic studies, which play an important role in information processing, is the investigation of astrocytes in neuronal models. This paper presents an efficient FPGA-based digital implementation of a spiking neuron model, known as the 2D Hindmarsh-Rose model, and neuron-astrocyte model. To avoid costly computations, the astrocyte and 2D Hindmarsh-Rose models were approximated. The approximation was performed based on multiple method such as the piecewise linear model (PWL) and the particle swarm optimization (PSO) method. As known, noisy mechanisms are stochastic processes which help to improve information processing in nonlinear dynamical systems, including neural systems, and results in more realistic behaviors. Therefore, we presented the noise implications for the approximated neuron-astrocyte models. By introducing two networks consisting of ten 2D Hindmarsh-Rose neurons, the role of the approximated astrocyte in regulation of the neural activities and noise tolerance of the neural networks was investigated. Accordingly, the feasibility of the digital implementation for the proposed 2D Hindmarsh-Rose neuron and the neuron-astrocyte models was studied. Experimental findings of the hardware synthesis and physical implementation on a field-programmable gate array (FPGA) were expounded for the modified spiking neuron model and the approximated astrocyte models with maximum clock frequencies of 247.35 MHz and 279.28 MHz, respectively, showed an increase by about 3.5 times in the frequency in both approximated models. The number of slice registers decreased by 22% and 20% in the proposed 2D Hindmarsh-Rose and astrocyte models, respectively. Also, the networks in the original and approximated 2D Hindmarsh-Rose neurons and astrocyte were synthesized on an FPGA platform. Maximum clock frequencies for both networks were 73.09 MHz and 182.18 MHz, respectively. Comparison of the synthesis results of the two networks showed decreases by 58% and 98% in the number of slice registers and the number of DSPs, respectively.