An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

被引：1

作者：

Xin Cheng ^{[1
]}

Yu Zhang ^{[1
]}

Guangjun Xie ^{[1
]}

Yizhong Yang ^{[1
]}

Zhang Zhang ^{[1
]}

机构：

[1] School of Electronic Science and Applied Physics, Hefei University of Technology

来源：

Journal of Semiconductors | 2018年 / 03期

基金：

中国国家自然科学基金;

关键词：

LDO; output capacitorless; ultra-low power; slew rate;

D O I：

暂无

中图分类号：

TM44 [稳定器];

学科分类号：

080801 ;

摘要：

An ultra-low power output-capacitorless low-dropout(LDO) regulator with a slew-rate-enhanced(SRE)circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging(or discharging) the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 m A and the corresponding variation of output voltage is less than 40 m V. Moreover, the measured line regulation and load regulation are 15.38 m V/V and 0.4 m V/m A respectively.

引用

页码：70 / 75

页数：6

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