Easy Test Generation PLAs

被引：0
|
作者：
闵应骅 [1 ]
机构：
[1] Chinese Academy of Railway Sciences
来源：
JournalofComputerScienceandTechnology | 1987年 / 01期
关键词：
test; ETG; Test;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Test Generation for large circuits may be extremely difficult.One of the approaches to alleviatingthis problem is to consider the difficulties during the design cycle.This paper proposes a design of EasyTest Generation Programmable Logic Arrays(ETG PLAs),for which test generation is basically notrequired,since a complete test set can be generated while the test is applied.This paper also presents aprocedure which makes a PLA an ETG PLA by following some design rules and providing reasonableextra hardware.
引用
收藏
页码：72 / 80
页数：9
相关论文
共 50 条
  • [1] COMPUTATIONAL-COMPLEXITY OF TEST-GENERATION FOR ETG PLAS
    MIN, YH
    MALAIYA, YK
    GUPTA, B
    IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1989, 136 (02): : 107 - 111
  • [2] Combined probabilistic testability calculation and compact test generation for PLAs
    Reppen, Bjorg
    Aas, Einar J.
    Journal of Electronic Testing: Theory and Applications (JETTA), 1991, 2 (03): : 215 - 227
  • [3] PROBABILISTIC ANALYSIS OF ALGORITHMS FOR STUCK-AT TEST-GENERATION IN PLAS
    FRANCO, J
    LECTURE NOTES IN CONTROL AND INFORMATION SCIENCES, 1992, 174 : 56 - 75
  • [4] FAULT ANALYSIS AND TEST GENERATION FOR PROGRAMMABLE LOGIC-ARRAYS (PLAS)
    OSTAPKO, DL
    HONG, SJ
    IEEE TRANSACTIONS ON COMPUTERS, 1979, 28 (09) : 617 - 627
  • [5] Minimal test set generation for fault diagnosis in R-valued PLAs
    Nagata, Y
    Miller, DM
    Mukaidono, M
    1998 28TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC - PROCEEDINGS, 1998, : 38 - 43
  • [6] Fault analysis and a unified design of PLAs for easy testability
    Sharam, Rajiv
    Rajashekhara, T.N.
    Computers and Electrical Engineering, 1988, 14 (1-2): : 53 - 63
  • [7] FAULT ANALYSIS AND A UNIFIED DESIGN OF PLAS FOR EASY TESTABILITY
    SHARMA, R
    RAJASHEKHARA, TN
    COMPUTERS & ELECTRICAL ENGINEERING, 1988, 14 (1-2) : 53 - 63
  • [8] GENERATION OF PLAS IN DYNAMIC CMOS TECHNOLOGY
    KUSKE, E
    LAWITZKY, G
    MICROPROCESSING AND MICROPROGRAMMING, 1985, 16 (2-3): : 191 - 191
  • [9] PROGRAMMABLE LOGIC ARRAYS WITH THE PROPERTIES OF EASY TEST GENERATION
    闵应骅
    Science China Mathematics, 1990, (12) : 1501 - 1518
  • [10] PROGRAMMABLE LOGIC ARRAYS WITH THE PROPERTIES OF EASY TEST GENERATION
    闵应骅
    ScienceinChina,SerA., 1990, Ser.A.1990 (12) : 1501 - 1518
12345