Energy-efficient and security-optimized AES hardware design for ubiquitous computing

Ubiquitous computing must incorporate a certain level of security.For the severely resource con-strained applications,the energy-efficient and small size cryptography algorithm implementation is a critical prob-lem.Hardware implementations of the advanced encryption standard (AES) for authentication and encryption are presented.An energy consumption variable is derived to evaluate low-power design strategies for battery-powered devices.It proves that compact AES architectures fail to optimize the AES hardware energy,whereas reducing invalid switching activities and implementing power-optimized sub-modules are the reasonable methods.Implemen-tations of different substitution box (S-Boxes) structures are presented with 0.25 μm 1.8 V CMOS (complementary metal oxide semiconductor) standard cell library.The comparisons and trade-offs among area,security,and power are explored.The experimental results show that Galois field composite S-Boxes have smaller size and highest security but consume considerably more power,whereas decoder-switch-encoder S-Boxes have the best power char-acteristics with disadvantages in terms of size and security.The combination of these two type S-Boxes instead of homogeneous S-Boxes in AES circuit will lead to optimal schemes.The technique of latch-dividing data path is analyzed,and the quantitative simulation results demonstrate that this approach diminishes the glitches effectively at a very low hardware cost.