Design and Implementation of Embedded Multiple-ISA Processor Based on RISC-V

被引:0
|
作者
Cheng, Yuan-Hu [1 ]
Huang, Li-Bo [1 ]
Cui, Yi-Jun [1 ]
Ma, Sheng [1 ]
Wang, Yong-Wen [1 ]
Sui, Bing-Cai [1 ]
机构
[1] College of Computer Science and Technology, National University of Defense Technology, Changsha,410073, China
来源
Tien Tzu Hsueh Pao/Acta Electronica Sinica | 2021年 / 49卷 / 11期
关键词
Program translators - Ecology - Reduced instruction set computing;
D O I
10.12263/DZXB.20201350
中图分类号
X17 [环境生物学];
学科分类号
071012 ; 0713 ;
摘要
Software ecology is one of the most critical factors restricting the development of RISC-V instruction set architecture. Allowing the RISC-V processor to directly run the ARM Thumb binary code can solve its software ecological problem in the embedded field to a certain extent. Based on the binary translation, this article realizes support for the ARM Thumb program and achieves comparable performance on the RISC-V processor with the lower area and power consumption overhead by using hardware to optimize ARM Thumb flag bits, branch instructions, and conditional execution. For the Embench benchmark suite, the average performance of the processor running ARM Thumb programs can reach 75.5% of directly running RISC-V programs. Compared with using only binary translation to support ARM Thumb, hardware optimization performance is improved by 3.1 times and hardware overhead is reduced by 7.8%. © 2021, Chinese Institute of Electronics. All right reserved.
引用
收藏
页码:2081 / 2089
相关论文
共 50 条
  • [21] Seesaw: A 4096-bit vector processor for accelerating Kyber based on RISC-V ISA extensions
    Zou, Xiaofeng
    Peng, Yuanxi
    Li, Tuo
    Kong, Lingjun
    Zhang, Lu
    PARALLEL COMPUTING, 2025, 123
  • [22] CNN Specific ISA Extensions Based on RISC-V Processors
    Yu, Xiang
    Yang, Zhijie
    Peng, Linghui
    Lin, Bo
    Yang, Wenjing
    Wang, Lei
    2022 5TH INTERNATIONAL CONFERENCE ON CIRCUITS, SYSTEMS AND SIMULATION (ICCSS 2022), 2022, : 116 - 120
  • [23] Maxpool operator for RISC-V processor
    Nevezi-Strango, David
    Rotar, Danut
    Valcan, Sorin
    Gaianu, Mihail
    2023 25TH INTERNATIONAL SYMPOSIUM ON SYMBOLIC AND NUMERIC ALGORITHMS FOR SCIENTIFIC COMPUTING, SYNASC 2023, 2023, : 246 - 250
  • [24] An Implementation of a World Grid Square Codes Generator on a RISC-V Processor
    Watanabe, Rei
    Tada, Jubee
    Sato, Keiichi
    Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021, 2021, : 309 - 312
  • [25] Design and Implementation of a RISC V Processor on FPGA
    Poli, Ludovico
    Saha, Sangeet
    Zhai, Xiaojun
    Mcdonald-Maier, Klaus D.
    2021 17TH INTERNATIONAL CONFERENCE ON MOBILITY, SENSING AND NETWORKING (MSN 2021), 2021, : 161 - 166
  • [26] Design and Implementation of Low-Power IoT RISC-V Processor with Hybrid Encryption Accelerator
    Yang, Sen
    Shao, Lian
    Huang, Junke
    Zou, Wanghui
    ELECTRONICS, 2023, 12 (20)
  • [27] Design of IOMMU Based on RISC-V
    Wang, Zhendao
    Ban, Guilong
    Hu, Jin
    Jiao, Xufeng
    Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences, 2024, 51 (06): : 187 - 194
  • [28] Secure Boot Design for a RISC-V Based SoC and Implementation on an FPGA
    Adiguzel, Yasin
    Yalcin, Siddika Berna Ors
    32ND IEEE SIGNAL PROCESSING AND COMMUNICATIONS APPLICATIONS CONFERENCE, SIU 2024, 2024,
  • [29] Implementation of Hardware Trace Buffer Module for RISC-V Processor Core
    Shveida, Bohdan
    Marcinek, Krzysztof
    Pleskacz, Witold A.
    2024 31ST INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM, MIXDES 2024, 2024, : 110 - 113
  • [30] RISC-V2: A Scalable RISC-V Vector Processor
    Patsidis, Kariofyllis
    Nicopoulos, Chrysostomos
    Sirakoulis, Georgios Ch
    Dimitrakopoulos, Giorgos
    2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,