Design and Implementation of Embedded Multiple-ISA Processor Based on RISC-V

Software ecology is one of the most critical factors restricting the development of RISC-V instruction set architecture. Allowing the RISC-V processor to directly run the ARM Thumb binary code can solve its software ecological problem in the embedded field to a certain extent. Based on the binary translation, this article realizes support for the ARM Thumb program and achieves comparable performance on the RISC-V processor with the lower area and power consumption overhead by using hardware to optimize ARM Thumb flag bits, branch instructions, and conditional execution. For the Embench benchmark suite, the average performance of the processor running ARM Thumb programs can reach 75.5% of directly running RISC-V programs. Compared with using only binary translation to support ARM Thumb, hardware optimization performance is improved by 3.1 times and hardware overhead is reduced by 7.8%. © 2021, Chinese Institute of Electronics. All right reserved.