Readout circuit noise analysis and low-noise design for piezoelectric micro-machined ultrasonic transducers with large parasitic capacitance

Readout circuits are fundamental components in many application systems that utilize piezoelectric micro-machined ultrasonic transducers (pMUTs). This study models the noise and signal transfer functions of trans-impedance amplifiers (TIAs), charge-sensitive circuits, and voltage-mode readout circuits in detail. A series of simulations and experiments were conducted to elucidate the advantages and disadvantages of these circuit types. Both theoretical and experimental results indicate that the intrinsic capacitance of large pMUTs can significantly degrade the quality of the readout signal. Furthermore, while the TIA-based readout circuit demonstrates clear gain advantages, it is also susceptible to considerable noise interference. This work proposes an improved readout circuit design that effectively mitigates noise interference while preserving the gain advantages of the TIA architecture. The implemented prototype circuit successfully reduces the noise from 73 mVp-p to 13 mVp-p.