Low power memristor circuit with electronically Tunable

This paper introduces a charge-controlled memristor emulator (MRE) circuit based on CMOS technology, utilizing the second-generation Current Controlled Current Conveyor (CCCII) as the active element. The proposed MRE circuit is designed as a grounded configuration, incorporating a resistor and a capacitor as passive elements. Mathematical analysis of the circuit was performed, and simulation studies using TSMC 180 nm technology and the LTspice program confirmed the expected pinch hysteresis curves characteristic of memristors. These curves were also obtained under various conditions and parameters to evaluate the circuit's robustness. To this end, temperature analyses, process corner analyses, and Monte Carlo simulations were performed. The pulse signal response of the proposed circuit was examined, demonstrating its capability to perform in incrementing and decrementing modes. The circuit supports a maximum operating frequency of 150 MHz and features a low power consumption of 2.76 mu W. Due to its nonlinear characteristics, proposed MRE is well-suited for chaotic applications. To illustrate this, the circuit was adapted to the Jerk system. Mathematical analyses of the proposed system were performed, and simulation studies in LTspice generated phase portraits that confirmed chaotic behavior. Finally, an experimental study has been realized to demonstrate to feasibility of the proposed MRE, by commercially available components, AD844 and AD633.