Passivating and low damaging plasma etching of GaN using Cl2 and SiCl4 for recessed gate MOSc-HEMT devices

被引:0
|
作者
Cascales, David [1 ,2 ]
Barros, Patricia Pimenta [1 ]
Martinez, Eugenie [1 ]
Ben Abbes, Riadh [2 ]
Salem, Bassem [2 ]
机构
[1] Univ Grenoble Alpes, CEA, F-38000 Grenoble, France
[2] Univ Grenoble Alpes, CNRS, CEA, Grenoble INP,LTM,LETI Minatec, F-38054 Grenoble, France
关键词
GaN; plasma etching; interface state; power electronics; OHMIC CONTACTS; SURFACE; DEPOSITION; FILMS; XPS;
D O I
10.1088/1361-6641/ad8303
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Plasma etching steps are critical for metal-oxide-semiconductor channel high electron mobility transistors gate fabrication as they can deteriorate electrical performances due to gallium nitride degradation. Adding SiCl4 to a low bias Cl-2 plasma in presence of a SiN hard mask environment forms a silicon-based passivation layer that protects GaN from nitrogen depletion (N/Ga = 1) as extracted from X-ray photoelecron spectroscopy measurements. The deposited layer is not removed by subsequent surface treatments that precede the gate dielectric deposition such as O-2 plasma and HCl. This nitrogen preservation as well as the passivation's presence result in a higher flat band voltage (V-FB) due to less positive charge generation at the GaN/dielectric interface. This SiCl4-based etching process could then be used as a 20 nm plasma etching finishing step in order to recover GaN surface after a fast and damaging trench formation process.
引用
收藏
页数:10
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