Minimal design of multi-stage reservoir based on small-world network

We will present a methodology of dividing a large single reservoir into number of small reservoirs and concatenating them in a multi-stage architecture. Our goal is to pursue the minimal design of multi-stage reservoir in terms of the reservoir size and the number of stages, while the performance is equivalent to a single reservoir having much larger number of nodes than the total number of nodes of multi-stage reservoir. A motivation behind this is to explore a good balance between the computational capability and downsizing hardware of photonic reservoir computing (RC) so that advanced photonic integrated circuits (PICs) technology such as multi-chip module and chiplet can afford in near future. To this end, we will pick up one of the multi-stage reservoir models and introduce small-world network instead of conventional random network reservoir to enable a systematic approach to synthesis of the optimum reservoir model. To validate the proposed methodology, we conduct benchmark tests, including both predictions and classification of time series data. We demonstrate that the proposed minimal design for the RC hardware allows a substantial downsizing without any loss of the performance. Finally, we will present a conceptual design of the minimal multi-stage reservoir for the photonic chiplet.