Warpage Investigation of Fan-Out Wafer-Level Packaging With Novel Thermosetting Films

With the continuous investment of significant manufacturers, fan-out packaging has already covered high-end high-density applications and low-end core applications, such as power management integrated circuits, RF transceivers, connection modules, audio/codec modules, radar modules, sensors, etc. Owing to TSMC's capacity in wafer-level fan-out packaging continues to expand, fan-out packaging remains a popular packaging solution for applications, such as InFO-AiP for 5G wireless communications and InFO-oS for high-performance computing. Unlike the design flaws of traditional WLP schemes, the number of I/O connections in FOWLP is unlimited. Therefore, FOWLP cuts individual dies from the entire wafer and coats them with epoxy molding compound (EMC). The foundry designed and fabricated the space allocations of each dies with an additional I/O connection. After that, redistribution layers (RDLs) are the classic method of interconnecting dies and solder joints rather than substrates. However, a significant problem and challenge in the engineering process is warpage, which is caused by differences in thermal expansion coefficients between dissimilar materials. Thermal annealing process (TAP) is an alternative technique to complete the curing of thermosetting films. Residual stress in thin films is of a major concern in the diaphragm molding. An excessive tensile stress can lead to film cracking, whereas a comprehensive stress can result in film bucking. Therefore, it is of great importance to identify a convenient technique to release the residual stress in a controlled manner during the fabrication of FOWLP. In this paper, combined with TAP and theory of residual stress release, we elucidate a novel process of FOWLP by adopting thermosetting films to realize warpage of 8 inch wafer can controlled within 2 mm in the whole process and 0.2 mm after molding process.