A novel 8T SRAM cell using PFC and PPC VS-CNTFET transistor

The 8T static random-access memory (SRAM) cell using carbon nanotube technology, positive feedback, and dynamic supply voltage scaling are presented in this work. Positive feedback strengthens the feedback loop and enhances the noise margin making SRAM cells less susceptible to disturbance and improving the stabilization of the cell by improving read and write timing response. Positive feedback control (PFC) adjusts the cell’s operating condition based on its current and external condition under varying conditions. The positive power supply controlled (PPC) technique in SRAM cell design improves the stability and leakage power consumption by adjusting the voltage level during the operation mode of the cell. The experiment with carbon nanotube field-effect transistor (CNTFET) offers higher drive current and lower power consumption compared to conventional silicon-based transistors. The performance of the 8T SRAM cell incorporating PFC and PPC transistor is investigated with Synopsys HSPICE using the Stanford CNFET model. The proposed SRAM cell architecture archives a 99.99% improvement in power consumption and delay product (PDP) compared to a conventional 6T SRAM cell. The static noise margin of 300 mV ensures better noise immunity and reliable retention of data. The mean value of power consumption is 43.19 nW showing a variance of 93.16 fW and a standard deviation (σ) of 305.2 nW and the mean value of delay is 14.71 ps showing a variance of 1.010 and a standard deviation (σ) of 10.05 ps. CNTFET 8T SRAM cell with the combination of positive feedback and dynamic feedback enhances the performance and efficiency of the memory cell under varying conditions.