Optimizing hardware-software co-design based on non-ideality in memristor crossbars for in-memory computing

The memristor crossbar, with its exceptionally high storage density and parallelism, enables efficient vector matrix multiplication (VMM), significantly improving data throughput and computational efficiency. However, its analog computing is vulnerable to issues like IR-drop, device-to-device (D2D) variation, and stuck-at-fault (SAF), leading to a substantial decrease in the inference accuracy of neural networks deployed on crossbars. This work presents a hardware-software co-design approach tailored to deal with memristor crossbar non-ideality. We introduce an end-to-end functional array simulator (FAST) for precise and ultra fast end-to-end training, mapping, and evaluation of neural networks on the memristor crossbar. Utilizing the sparsity of the memristor crossbar coefficient matrix, it achieves simulation with low storage and computational resource requirements, dynamically selecting the optimal solution to complete the process. It can also precisely simulate the impact of non-ideal effects such as IR-drop, retention, variation, SAF, and AD/DA precision. Using FAST, we assess memristor crossbar matrix operations under non-ideal conditions, identifying the max throughput and the most energy-efficient crossbar configurations. Additionally, we propose a comparator-based activation function modulation (CAFM) scheme and its corresponding hardware architecture with programmable activation function circuits to address the IR-drop issue, enabling low power and area overheads, resulting in the recovery of neural network accuracy by 54% or more. This is validated within FAST, demonstrating the success of our hardware-software optimization co-design.