Dynamic IGBT Compact Thermal Network Model Over Long Time Scales

被引:0
|
作者
Ma, Mingyao [1 ]
Zhang, Qian [1 ]
Guo, Weisheng [2 ,3 ]
Song, Qiwei [1 ]
机构
[1] Hefei Univ Technol, Natl Lab Renewable Energy Access Grid, Hefei 230009, Peoples R China
[2] City Univ Hong Kong, Dept Elect Engn, Hong Kong, Peoples R China
[3] City Univ Hong Kong, State Key Lab Terahertz & Millimeter Waves, Hong Kong, Peoples R China
基金
中国国家自然科学基金;
关键词
Insulated gate bipolar transistors; Degradation; Thermal degradation; Mathematical models; Junctions; Finite element analysis; Heating systems; Solid modeling; Packaging; Manufacturing; Chip solder degradation; compact thermal network model; finite-element method (FEM); insulated gate bipolar transistor (IGBT); long time scale; SOLDER FATIGUE; JUNCTION TEMPERATURE; CAUER MODEL; POWER; MODULE; RELIABILITY; DIAGNOSTICS; VOIDS;
D O I
10.1109/TCPMT.2024.3513323
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The cause of failures in insulated gate bipolar transistor (IGBT) modules is primarily attributed to temperature-related factors. Accurately estimating the junction temperature of IGBT modules is crucial for enhancing their reliability. Currently, thermal network models stand as commonly used tools for estimating the junction temperature of IGBT modules. However, prevailing thermal models exhibit certain limitations in accurately predicting the junction temperature, particularly when considering the degradation of chip solder within IGBT modules. This article presents a practical degradation model of the chip solder layer, establishing a functional correlation between the chip solder degradation rate and the number of power cycles. A dynamic compact thermal network model over long time scales is established, and the method for thermal parameter extraction is discussed. The finite-element simulation and experimental results show that the dynamic compact thermal network model can accurately estimate the junction temperature.
引用
收藏
页码:123 / 130
页数:8
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