Growth and characterization of SiGe/Si superlattice for vertically stacked DRAM

被引:0
|
作者
Wang, Hailing [1 ]
Wang, Xiangsheng [1 ]
Song, Yanpeng [1 ]
Liu, Xiaomeng [1 ]
Zhang, Ying [1 ]
Liu, Xinyou [1 ]
Wang, Guilei [1 ]
Zhao, Chao [1 ]
机构
[1] Beijing Superstring Acad Memory Technol, Beijing 100176, Peoples R China
关键词
STRAIN RELAXATION; LATTICE MISMATCH; SI; DISLOCATIONS; INTERDIFFUSION; GE;
D O I
10.1007/s10854-024-14167-y
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this study, SiGe/Si superlattices films (SLs) with different tiers were epitaxially grown by reduced pressure chemical vapor deposition (RPCVD) on 300 mm Si (001) substrate. Crystal quality of SiGe/Si SLs films (relaxation, surface roughness, interface characteristics and dislocation density) were quantitative evaluated by various characterization methods. A systematic investigation was conducted on the transition process of the SiGe/Si SLs films from full strain to relaxation state with increasing stacking layers. And, the variation trend of dislocation density and surface roughness with increasing stacking layers is studied. Additionally, we examined the changes in crystal quality and dislocation density of these SLs films after thermal annealing (20 min, @700 degrees C), and all the films exhibit higher strain relaxation by generating more misfit dislocations propagating in-plane. This study provides guidance and reference for the regulation of process parameters and the design of superlattice structure in vertically stacked DRAM.
引用
收藏
页数:11
相关论文
共 50 条
  • [21] Vertically stacked Si nanostructures for biosensing applications
    Buitrago, Elizabeth
    Fernandez-Bolanos, M.
    Ionescu, A. M.
    MICROELECTRONIC ENGINEERING, 2012, 97 : 345 - 348
  • [22] Block-by-block growth of single-crystalline Si/SiGe superlattice nanowires
    Wu, YY
    Fan, R
    Yang, PD
    NANO LETTERS, 2002, 2 (02) : 83 - 86
  • [23] Impact of Interconnections on Vertically Stacked 20 μm-thick DRAM Chips
    Murugesan, M.
    Fukushima, T.
    Bea, J. C.
    Hashimoto, H.
    Koyanagi, M.
    Tanikawa, S.
    Tanaka, T.
    2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2016, : 50 - 55
  • [24] A comparison of thin film microrefrigerators based on Si/SiGe superlattice and bulk SiGe
    Ezzahri, Y.
    Zeng, G.
    Fukutani, K.
    Bian, Z.
    Shakouri, A.
    MICROELECTRONICS JOURNAL, 2008, 39 (07) : 981 - 991
  • [25] Optimization and analysis of Si/SiGe strained vertically stacked heterostructure on insulator FeFinFET for high performance analog and RF applications
    Verma, Kajal
    Chaujar, Rishu
    PHYSICA SCRIPTA, 2024, 99 (11)
  • [26] Stacked Josephson junction based on Nb/Si superlattice
    I. Vávra
    P. Lobotka
    J. Dérer
    Ŝ. Gaži
    L. R. Wallenberg
    V. Holý
    J. Kuběna
    J. Sobota
    Journal of Low Temperature Physics, 1997, 106 : 373 - 379
  • [27] Stacked Josephson junction based on Nb/Si superlattice
    Vavra, I
    Lobotka, P
    Derer, J
    Gazi, S
    Holy, V
    Kubena, J
    Sobota, J
    JOURNAL OF LOW TEMPERATURE PHYSICS, 1997, 106 (3-4) : 373 - 379
  • [28] Vertically stacked (Nb/Si)*10 Josephson junction
    Lobotka, P
    Vavra, I
    Gazi, S
    Derer, J
    CZECHOSLOVAK JOURNAL OF PHYSICS, 1996, 46 : 701 - 702
  • [29] Vertically-stacked on-chip SiGe/BiCMOS/RFCMOS coplanar waveguides
    Woods, W
    Tretiakov, Y
    Vaed, K
    Ahlgren, D
    Rascoe, J
    Singh, R
    PROCEEDINGS OF THE IEEE 2004 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2004, : 245 - 247
  • [30] Transport Properties of 3D Vertically Stacked SiGe and SiGeC Nanowires
    Diab, A.
    Saracco, E.
    Ionica, I.
    Bonafos, C.
    Damlencourt, J. F.
    Cristoloveanu, S.
    ADVANCED SEMICONDUCTOR-ON-INSULATOR TECHNOLOGY AND RELATED PHYSICS 15, 2011, 35 (05): : 157 - 162