Features of TCAD and SPICE Simulation of a Charged Particle Impact into a 6T SRAM Cell Manufactured Using the CMOS 28-nm Technology Node

被引：0

作者：

Petrosyants, K.O. ^{[1
,2
]}

Silkin, D.S. ^{[1
]}

Popov, D.A. ^{[1
]}

Ismail-Zade, M.R. ^{[1
]}

Kharitonov, I.A. ^{[1
]}

Pereverzev, L.E. ^{[3
]}

Morozov, A.A. ^{[3
]}

Turgenev, P.V. ^{[3
]}

机构：

[1] National Research University Higher School of Economics, Moscow, Russia

[2] Institute for Design Problems in Microelectronics, Russian Academy of Sciences, Moscow, Russia

[3] ООО AlphaCHIP, Moscow, Russia

来源：

Russian Microelectronics | 2024年 / 53卷 / 07期

关键词：

16;

D O I：

10.1134/S1063739724700823

中图分类号：

学科分类号：

摘要：

引用

页码：737 / 743

页数：6

共 26 条

[11] A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology
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[18] A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
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[19] A Novel Embedded Design using High Performance and Low Leakage 6T SRAM Cell based on Word Decoding Scheme at 90 nm Technology
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[20] Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology
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