Hardware Area Efficient and Real-Time FPGA Implementation of PHMMRGB

For encryption applications on embedded systems, operating in real-time while using minimal system resources is essential. It is expected that efficient and rapid encryption of high-resolution images is to be accomplished with limited hardware resources. Therefore, to ensure the desired efficiency of encryption of high-resolution images, the system must possess a digital architecture capable of achieving high speeds with minimal hardware resources. This study considered the limitations of a hardware architecture for an image encryption algorithm based on the Profile Hidden Markov Model called PHMMRGB. The proposed architecture is relatively simple in comparison to its alternatives. The hardware architecture, designed with the objective of using minimal resources, has been implemented on an FPGA. Based on the results of the proposed architecture, it is believed that the implementation of the specified method on an FPGA would yield high efficiency. Experiments conducted using large-sized satellite images confirmed this expectation.