A 44.3 TOPS/W SRAM Compute-in-Memory With Near-CIM Analog Memory and Activation for DAC/ADC-Less Operations

被引：1

作者：

Chen, Peiyu ^{[1
]}

Wu, Meng ^{[1
]}

Zhao, Wentao ^{[1
]}

Ma, Yufei ^{[1
]}

Jia, Tianyu ^{[1
]}

Ye, Le ^{[1
]}

机构：

[1] Peking Univ, Sch Integrated Circuits, Beijing 100871, Peoples R China

来源：

IEEE SOLID-STATE CIRCUITS LETTERS | 2024年 / 7卷

基金：

中国国家自然科学基金;

关键词：

In-memory computing; Analog memory; Computer architecture; Common Information Model (computing); Solid state circuits; Capacitors; Random access memory; analog nonlinearity activation; compute-in-memory (CIM); DAC/ADC-less; SRAM;

D O I：

10.1109/LSSC.2024.3418099

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this letter, we present an analog compute-in-memory (CIM) macro design which incorporates near-CIM analog memory and nonlinearity activation unit (NAU) to alleviate the DAC/ADC power bottleneck. Fully differential analog memory is designed with switched capacitor storage circuits. Activation function, e.g., rectified linear unit, is also performed in analog domain in NAU. The CIM macro is fabricated using TSMC 55-nm technology, with a peak macro-level efficiency of 44.3 TOPS/W and a system energy efficiency of 27.7 TOPS/W for analog input and output with 4-bit weight. The near-CIM analog memory and NAU solution brings 76.0% energy reduction compared with DAC/ADC solution, which contributes 1.34x to 2.37x energy efficiency improvement.

引用

页码：299 / 302

页数：4

共 25 条

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