共 50 条
- [35] Demythisation of interfaces in OOP ROMANIAN JOURNAL OF INFORMATION TECHNOLOGY AND AUTOMATIC CONTROL-REVISTA ROMANA DE INFORMATICA SI AUTOMATICA, 2020, 30 (04): : 73 - 84
- [38] Guidelines for safe simulation and synthesis of implicit style Verilog 1998 INTERNATIONAL VERILOG HDL CONFERENCE AND VHDL INTERNATIONAL USERS FORUM, PROCEEDINGS, 1998, : 59 - 66