HEURISTIC PROCEDURE FOR ORDERING MOS ARRAYS.

被引：0
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作者：
Yoshizawa, H.
Kawanishi, H.
Kani, K.
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| 1975年
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摘要：
The problem of minimizing chip area under one-dimensional MOS array layout method is treated as a combinatorial ordering problem. The heuristic procedure, consisting of initial ordering and iterative improvement, is presented. Based on computational experience, it is recognized that this procedure can yield considerable improvements, compared to manual design methods.
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页码：384 / 393
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