Computing in memory architectures for digital image processing

被引：0
|
作者：
Roth, Luke [1 ]
Coraor, Lee [1 ]
Landis, David [1 ]
Hulina, Paul [1 ]
Deno, Scott [1 ]
机构：
[1] Pennsylvania State Univ, University Park, United States
来源：
Records of the IEEE International Workshop on Memory Technology, Design and Testing | 1999年
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：8 / 15
相关论文
共 50 条
  • [1] Evaluation of computing in memory architectures for digital image processing applications
    Pennsylvania State Univ, University Park, United States
    Proc IEEE Int Conf Comput Des VLSI Comput Process, (146-151):
  • [2] Efficient computing architectures for processing digital image data
    Sundaram, R
    APPLICATIONS OF DIGITAL IMAGE PROCESSING XXVII, PTS 1AND 2, 2004, 5558 : 80 - 86
  • [3] COMPUTING PROJECTIONS OF DIGITAL IMAGES IN IMAGE-PROCESSING PIPELINE ARCHITECTURES
    SANZ, JLC
    HINKLE, EB
    IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1987, 35 (02): : 198 - 207
  • [4] Image processing and computing for digital holography with ImageJ
    Castaneda, Raul
    Piedrahita-Quintero, Pablo
    Garcia-Sucerquia, Jorge
    OPTICA PURA Y APLICADA, 2015, 48 (02): : 77 - 84
  • [5] DIGITAL COMPUTING IN HOLOGRAPHY AND IMAGE-PROCESSING
    CAULFIELD, HJ
    PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS, 1985, 528 : 83 - 87
  • [6] PARALLEL ARCHITECTURES FOR DIGITAL OPTICAL CELLULAR IMAGE-PROCESSING
    HUANG, KS
    KUZNIA, CB
    JENKINS, BK
    SAWCHUK, AA
    PROCEEDINGS OF THE IEEE, 1994, 82 (11) : 1711 - 1723
  • [7] HIGH-SPEED ARCHITECTURES FOR DIGITAL IMAGE-PROCESSING
    VENETSANOPOULOS, AN
    TY, KM
    LOUI, ACP
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1987, 34 (08): : 887 - 896
  • [8] Signal Processing Methods to Enhance the Energy Efficiency of In-Memory Computing Architectures
    Sakr, Charbel
    Shanbhag, Naresh R.
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2021, 69 (69) : 6462 - 6472
  • [9] Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units
    Elbtity, Mohammed E.
    Reidy, Brendan
    Amin, Md Hasibul
    Zand, Ramtin
    PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2023, GLSVLSI 2023, 2023, : 607 - 612
  • [10] Cache write generate for parallel image processing on shared memory architectures
    Wittenbrink, CM
    Somani, AK
    Chen, CH
    IEEE TRANSACTIONS ON IMAGE PROCESSING, 1996, 5 (07) : 1204 - 1208
12345