OPTIMIZATION OF LDD MOSFET'S USING COUPLED 2-D SIMULATIONS.

During the design of p-channel LDD (lightly doped drain) devices for a CMOS technology, it was discovered that conventional LDD spacer design used for n-devices fails to give LDD structure to p-devices. Much wider spacers are required to create LDD p-channel devices. Detailed study of anisotropic etching of oxide used to define the LDD spacers showed that the spacers are not completely vertical and boron implant used in p** plus source-drain region of p-devices scatters underneath the spacers. A complete two-dimensional computer simulation of the process and resulting device structure was done using SAMPLE (etching and lithography simulator), MEMBRE (two-dimensional process simulator) and PISCES (two-dimensional device simulator) in coupled form. Implant doses, temperature cycles, and spacer widths were optimized for breakdown voltage, Miller capacitance, and ID//S//A//T for both n- and p-devices simultaneously. Experimental data agreed well with the simulations.