COMPARISON OF FINE-DIMENSION SILICON-ON-SAPPHIRE AND BULK-SILICON COMPLEMENTARY MOS DEVICES AND CIRCUITS.

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作者
Brassington, Michael P. [1 ]
Lewis, Alan G. [1 ]
Partridge, Susan L. [1 ]
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[1] GEC, Research Lab, Wembley, Engl, GEC, Research Lab, Wembley, Engl
关键词
INTEGRATED CIRCUITS - Testing - SEMICONDUCTING SILICON - Charge Carriers - SEMICONDUCTOR DEVICE MANUFACTURE - Silicon on Sapphire Technology - SUBSTRATES;
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摘要
The fabrication of fine-dimension silicon-gate MOS devices on both silicon-on-sapphire and bulk-silicon substrates has made possible a direct comparison of the electrical characteristics of devices based on these technologies. The same CMOS test chip design was used in both cases and provided both n- and p-channel devices having gate dimensions ranging down to submicrometer levels. Extensive electrical evaluation of the resulting devices has permitted a quantitative comparison of carrier mobilities, short- and narrow-channel threshold voltage shifts, punchthrough, and subthreshold characteristics for SOS and bulk-silicon technologies. The effect of epitaxial film thickness on these properties for SOS devices is also discussed. An anomalous narrow-channel threshold voltage shift effect is observed in SOS devices and is explained in terms of parasitic device characteristics. The general conclusion based on the observations made is that short- and narrow-channel effects in SOS devices are significantly less of a problem than in bulk silicon devices at these gate dimensions. At 1- mu m dimensions the propagation delay of SOS CMOS circuits is 60% lower than that of equivalent bulk-silicon CMOS circuits.
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页码:1858 / 1867
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