共 50 条
- [6] Fast and processor efficient parallel matrix multiplication algorithms on a linear array with a reconfigurable pipelined bus system IEEE Trans Parallel Distrib Syst, 8 (705-720):
- [7] Quicksort on a linear array with a reconfigurable pipelined bus system SECOND INTERNATIONAL SYMPOSIUM ON PARALLEL ARCHITECTURES, ALGORITHMS, AND NETWORKS (I-SPAN '96), PROCEEDINGS, 1996, : 313 - 319
- [9] Reconfigurable Digital/Analog processor array for the simulation of gene regulatory networks IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS,, 2006, : 552 - +