New architecture for high-speed neural network LSI

A sparse memory access architecture is proposed to achieve a high-computational-speed neural network LSI. The architecture uses two key techniques, compressible synapse weight neuron calculation and differential neuron operation, to reduce the number of accesses to synapse weight memories and the number of neuron calculations without any accuracy penalty. Out test chip contains 96 parallel data-driven 22b processing units and 12,288 synapse weight (16b) memories. In a pattern recognition example, the number of memory accesses and neuron calculations were reduced to 0.87% of that in the conventional method and the practical performance was 18 billion connections per second (GCPS).