HIERARCHICAL LOOSE ROUTING FOR GATE ARRAYS.

被引：0
|
作者：
Winter, Klaus
Mlynski, Dieter A.
机构：
来源：
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1986年 / CAD-6卷 / 05期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
INTEGRATED CIRCUITS, LSI
引用
下载
收藏
相关论文
共 50 条
  • [1] HIERARCHICAL LOOSE ROUTING FOR GATE ARRAYS
    WINTER, K
    MLYNSKI, DA
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1987, 6 (05) : 810 - 819
  • [2] Gate Arrays.
    Johansen, Eivind
    Elektronikcentralen (Report) ECR, 1983, : 1 - 98
  • [3] MASTER2: A HIERARCHICAL LAYOUT SYSTEM FOR GATE ARRAYS.
    Yabe, Shoji
    Nomura, Minoru
    Takano, Nobuo
    Kawanishi, Hiroshi
    Yoshizawa, Hitoshi
    Kato, Haruo
    Noda, Shigeo
    NEC Research and Development, 1984, (74): : 24 - 30
  • [4] AGAs - Alterable Gate Arrays.
    Krug, Heinz
    Elektronik Munchen, 1982, 31 (23): : 73 - 74
  • [5] DATA ROUTING AND TRANSPOSITIONS IN PROCESSOR ARRAYS.
    Jesshope, C.R.
    ICL technical journal, 1980, 2 (02): : 191 - 206
  • [6] Optical routing with liquid crystal arrays.
    Wilkinson, TD
    Crossland, WA
    OPTOELECTRONIC AND WIRELESS DATA MANAGEMENT, PROCESSING, STORAGE, AND RETRIEVAL, 2001, 4534 : 64 - 69
  • [7] FUJITSU OFFERS VERSATILE RANGE OF GATE ARRAYS.
    Honma, Akira
    JEE, Journal of Electronic Engineering, 1983, 20 (197): : 50 - 52
  • [8] GATE OXIDE INTEGRITY OF NMOS TRANSISTOR ARRAYS.
    Swartz, G.A.
    IEEE Transactions on Electron Devices, 1986, ED-33 (11) : 1826 - 1829
  • [9] REVIEW OF BUILT-IN TEST METHODOLOGIES FOR GATE ARRAYS.
    Totton, K.A.E.
    IEE Proceedings I: Solid State and Electron Devices, 1985, 132 (2 pt 1): : 121 - 129
  • [10] A Spiffy tool for the simultaneous placement and global routing for three-dimensional field-programmable gate arrays.
    Karro, J
    Cohoon, JP
    NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1999, : 230 - 231
12345