共 50 条
- [1] Reduced latency IEEE floating-point standard adder architectures 14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 1999, : 35 - 42
- [2] Reduced latency IEEE floating-point standard adder architectures Proceedings - Symposium on Computer Arithmetic, 1999, : 35 - 42
- [5] A CAD tool for scalable, variable architecture floating-point adder generator 2006 IEEE INTERNATIONAL CONFERENCE ON COMPUTER SYSTEMS AND APPLICATIONS, VOLS 1-3, 2006, : 74 - 79
- [6] A study on the floating-point adder in FPGAs 2006 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-5, 2006, : 1591 - +
- [7] A Redundant Decimal Floating-Point Adder 2010 CONFERENCE RECORD OF THE FORTY FOURTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS (ASILOMAR), 2010, : 1144 - 1147
- [8] Low-Latency VLSI Architecture of a 3-Input Floating-Point Adder 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 180 - 183