On-chip test scheme for SRAMs

被引：0
|
作者：
Lala, P.K. [1 ]
Walker, A. [1 ]
机构：
[1] North Carolina A&T State Univ, Greensboro, United States
来源：
| 1994年
关键词：
Random access storage;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：16 / 20
相关论文
共 50 条
  • [1] A scheme for multiple on-chip signature checking for embedded SRAMS
    Abdulla, MF
    Ravikumar, CP
    Kumar, A
    JOURNAL OF SYSTEMS ARCHITECTURE, 2000, 46 (02) : 181 - 199
  • [2] An On-Chip Sensor to Monitor NBTI Effects in SRAMs
    Ceratti, A.
    Copetti, T.
    Bolzani, L.
    Vargas, F.
    Fagundes, R.
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2014, 30 (02): : 159 - 169
  • [3] An On-Chip Sensor to Monitor NBTI Effects in SRAMs
    A. Ceratti
    T. Copetti
    L. Bolzani
    F. Vargas
    R. Fagundes
    Journal of Electronic Testing, 2014, 30 : 159 - 169
  • [4] On-chip multibit-test scheme for VLSI memories
    Hidaka, Hideto
    Fujishima, Kazuyasu
    Kumanoya, Masaki
    Miyatake, Hideshi
    Dosaka, Katsumi
    Nishimura, Yasumasa
    Yoshihara, Tsutomu
    Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), 1988, 71 (09): : 78 - 87
  • [5] AN EFFICIENT ON-CHIP DETERMINISTIC TEST PATTERN GENERATION SCHEME
    DAS, AK
    CHAUDHURI, PP
    MICROPROCESSING AND MICROPROGRAMMING, 1989, 26 (03): : 195 - 204
  • [6] On-Chip Source Synchronous Interface Timing Test Scheme with Calibration
    Kim, Hyunjin
    Abraham, Jacob A.
    DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2012), 2012, : 1146 - 1149
  • [7] An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring
    Yi, Hyunbean
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2013, 13 (01) : 71 - 78
  • [8] An at-speed scan test scheme using on-chip PLL
    Key Laboratory of Computer System and Architecture, Chinese Academy of Sciences, Beijing 100080, China
    不详
    不详
    Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao, 2007, 3 (366-370):
  • [9] A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs
    Medeiros, G. C.
    Bolzani Poehls, L. M.
    Taouil, M.
    Luis Vargas, F.
    Hamdioui, S.
    MICROELECTRONICS RELIABILITY, 2018, 88-90 : 355 - 359
  • [10] A scheme for on-chip timing characterization
    Datta, Ramyanshu
    Carpenter, Gary
    Nowka, Kevin
    Abraham, Jacob A.
    24TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2006, : 24 - +
12345