MOS ISOLATION TECHNOLOGY.

被引：0

作者：

Oldham, W.G. ^{[1
]}

Shacham-Diamand, Y. ^{[1
]}

Pai, P.L. ^{[1
]}

Young, K. ^{[1
]}

Sutardja, P. ^{[1
]}

机构：

[1] Univ of California, Berkeley, Dep of, Electrical Engineering &, Computer Sciences, Berkeley, CA, USA, Univ of California, Berkeley, Dep of Electrical Engineering & Computer Sciences, Berkeley, CA,

来源：

Physica B: Physics of Condensed Matter & C: Atomic, Molecular and Plasma Physics, Optics | 1984年 / 129 B-C卷 / 1-3期

关键词：

LOGIC DEVICES - Gates;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Local oxidation with self-aligned field threshold implant has become pervasive as the technique for device isolation in Si-gate technology. As NMOS is replaced by CMOS, this LOCOS technology has been adapted, though with difficulty. Primarily because of poor space utilization, alternatives to LOCOS are now being pursued in a number of laboratories. In this paper the goals and limitations of isolation technology are reviewed, and several alternatives examined. Based on this examination, the authors suggest that in the near future, evolutionary advances in LOCOS will be adequate. In the longer term, the greatest promise is offered by a technique involving etching and refilling trenches in the substrate. 32 refs.

引用

页码：53 / 65

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