BRANCH-PROCESSING INSTRUCTION CACHE.

This article teaches a novel instruction fetching mechanism designed for computer architecture which processes branch instructions while fetching other instructions, thereby eliminating most of the so-called branch penalty. The organization of the mechanism consists of an instruction cache, a directory integral with the cache arrays, and associated branch processing logic and dataflow which assumes the existence of a fixed-point processing unit and a floating-point processing unit to which non-branch instructions will be shipped. For the purposes of illustration, the instruction cache is logically organized as a 2-way set associative, 8KB capacity, 64B linesize cache.