CONTENT ADDRESSABLE MEMORY CIRCUIT USING JOSEPHSON JUNCTIONS.

被引：0

作者：

Morisue, M. ^{[1
]}

Kaneko, M. ^{[1
]}

Hosoya, H. ^{[1
]}

机构：

[1] Saitama Univ, Urawa, Jpn, Saitama Univ, Urawa, Jpn

来源：

IEEE Transactions on Magnetics | 1986年 / MAG-23卷 / 02期

关键词：

JOSEPHSON MULTIRESPONSE RESOLVER - JOSEPHSON NDRO MEMORY CELLS;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A content-addressable memory circuit using Josephson NDRO memory cells, which include a novel Josephson multiresponse resolver, is described. The memory circuit performs the searching functions such as coincidence, incoincidence and don't-care function, in addition to the conventional functions of writing and reading. Simulation results show that the cycle time of memory operation is 60 ps, power dissipation is 0. 28 mu W/cell and the cycle time of the multi-response resolver operation is 153 ps.

引用

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