Developing verification methodologies as FPGAs take over from gate arrays

被引：0

作者：

Sevcik, Rich ^{[1
]}

机构：

[1] Xilinx, Inc

来源：

Electronic Engineering (London) | 2000年 / 72卷 / 885期

关键词：

Application specific integrated circuits - Computer aided software engineering - Computer hardware description languages - Computer simulation - Computer software reusability - Error detection - Field programmable gate arrays - Integrated circuit testing - Logic gates - Table lookup;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Verification has always been an integral part of the FPGA design flow. In fact, engineers consider design verification as the most critical task in successfully creating complex designs and decreasing time to market. At present, various verification strategies, from which engineers can choose from are already available.

引用

页码：95 / 96

共 50 条

[1] Developing verification methodologies as FPGAs take over from gate arrays
Sevcik, B
ELECTRONIC ENGINEERING, 2000, 72 (885): : 95 - +
[2] Gate arrays to merge with FPGAs
Myrvaagnes, R
ELECTRONIC PRODUCTS MAGAZINE, 1996, 39 (05): : 18 - 18
[3] FPGAS AND DENSE EPLDS CHALLENGE GATE ARRAYS
BURSKY, D
ELECTRONIC DESIGN, 1995, 43 (14) : 69 - &
[4] FPGAS CHALLENGE GATE ARRAYS FOR SYSTEM FUNCTIONS
DONLIN, M
COMPUTER DESIGN, 1995, 34 (08): : 50 - 52
[5] PLDS, FPGAS, GATE ARRAYS - WEIGHING THE DIFFERENCES
FARRELL, L
COMPUTER DESIGN, 1990, 29 (16): : 19 - &
[6] Fast, flexible, dense FPGAs zero in on gate arrays
Dipert, B
EDN, 1997, 42 (05) : 18 - 18
[7] GATE ARRAYS FACE ONSLAUGHT OF DENSE AND FLEXIBLE FPGAS
BURSKY, D
ELECTRONIC DESIGN, 1995, 43 (13) : 85 - &
[8] Design issues in field programmable gate arrays (FPGAs)
Abd-El-Barr, M
Vranesic, Z
ICM'99: ELEVENTH INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, 1999, : 169 - 172
[9] FPGAs and gate arrays play tug of war for design wins
Donlin, M
COMPUTER DESIGN, 1996, 35 (05): : 70 - &
[10] IMPROVED ARRAY EFFICIENCY LETS FPGAS CHALLENGE GATE ARRAYS
BURSKY, D
ELECTRONIC DESIGN, 1995, 43 (18) : 91 - &

← 1 2 3 4 5 →