共 50 条
- [1] TOP: an algorithm for three-level combinational logic optimisation IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2004, 151 (04): : 307 - 314
- [3] Fast three-level logic minimization based on autosymmetry 39TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2002, 2002, : 425 - 430
- [6] Minimization of the number of links in three-level hierarchical telecommunication networks Electronics and Communications in Japan, Part I: Communications (English translation of Denshi Tsushin Gakkai Ronbunshi), 1994, 77 (11): : 38 - 48
- [7] Analysis and Minimization of Neutral Current of Three-Level PWM Inverter 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING AND INFORMATICS (ICEEI 2013), 2013, 11 : 502 - 509
- [9] MINIMAL 3-LEVEL COMBINATIONAL CIRCUITS - 2-LEVEL MULTIPLE-OUTPUT MINIMIZATION PROBLEM DIGITAL PROCESSES, 1979, 5 (1-2): : 73 - 97
- [10] Reducing the logic-level of the combinational circuits Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design & Computer Graphics, 1997, 9 (01):