Design of 1 GHz 0.5 μm CMOS low noise amplifier

被引：0

作者：

Yao, Fei ^{[1
]}

Cheng, Buwen ^{[1
]}

机构：

[1] Lab. on Integrated Optoelectronics, Inst. of Semi-conduct., Chinese Acad. of Sci., Beijing 100083, China

来源：

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors | 2004年 / 25卷 / 10期

关键词：

CMOS integrated circuits - Design - Gain measurement - Integrated circuit layout - Semiconductor device models;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A 1 GHz CMOS low noise amplifier (LNA) is presented, which is implemented in TSMC 0.5 μm CMOS technology. Optimized by the Hspice software, the following parameters are achieved: with a 2.5 V voltage supply, the operation current is 6 mA. The power is lower than 15 mW, the gain is larger than 10 dB, the noise figure is lower than 2 dB, the IIP3 is larger than 10 dBm, while the input reflection is less than -50 dB at 1 GHz.

引用

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页码：1291 / 1295

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