VIRTUAL GRID SYMBOLIC LAYOUT.

被引:0
|
作者
Weste, Neil
机构
关键词
Compilation and indexing terms; Copyright 2025 Elsevier Inc;
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:225 / 233
相关论文
共 50 条
  • [1] TOPOLOGIZER: AN EXPERT SYSTEM TRANSLATOR OF TRANSISTOR CONNECTIVITY TO SYMBOLIC CELL LAYOUT.
    Kollaritsch, Paul W.
    Weste, Neil H.E.
    IEEE Journal of Solid-State Circuits, 1984, SC-20 (03) : 799 - 804
  • [2] Testability of IC Layout.
    Barke, Erich
    NTZ. Nachrichtentechnische Zeitschrift, 1981, 34 (11): : 758 - 766
  • [3] 'GZP' ALGORITHM IN LAYOUT.
    Cook, P.W.
    Hsieh, H.H.
    1600, (26):
  • [4] GATE MATRIX LAYOUT.
    Wing, Omar
    Huang, Shuo
    Wang, Rui
    1600, (CAD-4):
  • [5] ISOSONIC TEMPLATES FOR PLANT LAYOUT.
    Hudec, Edward J.R.
    Kishel, Chester J.
    1975, 7 (04): : 422 - 426
  • [6] KEYBOARD CURSOR CONTROL LAYOUT.
    Williams, J.A.
    IBM technical disclosure bulletin, 1983, 26 (04): : 1967 - 1968
  • [7] AUTOMATED SYNTHESIS OF IC LAYOUT.
    Rathmell, J.G.
    Journal of Electrical and Electronics Engineering, Australia, 1983, 3 (04): : 257 - 265
  • [8] PROGRESSIVE DIE WITH ECONOMICAL STRIP LAYOUT.
    Muradov, N.S.
    Kasimov, Z.A.
    Sokiryanskaya, L.S.
    Soviet electrical engineering, 1986, 57 (02):
  • [9] SIMULATING THE COMPLEXITY OF REGULAR VLSI LAYOUT.
    Leung, Yu-Ying J.
    Shanblatt, Michael A.
    IEEE Journal of Solid-State Circuits, 1987, 23 (01)
  • [10] ONE-DEVICE CELL LAYOUT.
    Kruggel, R.H.
    IBM Technical Disclosure Bulletin, 1973, 15 (12): : 3751 - 3752