BOUNDARY-SCAN TECHNIQUE TARGETS BOARD-LEVEL TESTABILITY.

While much attention has been focused on the need for device-level testability, the issue of board-level testability has lingered in the background. An emerging standardization effort may change all that by encouraging the addition of boundary-scan cells to both standard and application-specific ICs. The boundary-scan concept calls for the addition of shift-register latches to the functional I/O pins of a device. Contained within boundary-scan cells, these latches are interconnected to form a boundary-scan path with a serial input and output. The boundary-scan concept was originated by Philips (Eindhoven, The Netherlands) and is now under development by the Joint Test Action Group (JTAG), an ad hoc organization of European and U. S. manufacturers.